The use of metal-induced dopant activation (MIDA) in amorphous Germanium (α-Ge) (Germanium is a Group IV element) is a known process. For example, reference can be made to Jin-Hong Park, M. Tada, D. Kuzum, P. Kapur, H-.Y. Yu, H-.S. Philip Wong, and K. C. Saraswat, “Low Temperature (≦380° C.) and High Performance Ge CMOS Technology with Novel Source/Drain by Metal-Induced Dopants Activation and High-K/Metal Gate Stack for Monolithic 3D Integration,” IEEE International Electron Devices Meeting (IEDM) 2008 Technical Digest, pp. 389-392, San Francisco, Calif., Dec. 15-17, 2008; and Jin-Hong Park, D. Kuzum, M. Tada and K. C. Saraswat, “High Performance Germanium N+/P and P30/N junction diodes formed at Low Temperature (<380° C.) using Metal-Induced Dopant Activation”, Applied Physics Letters 93, 193507 (2008). Reference can also be made to Jin-Hong Park, M. Tada, Woo-Shik Jung, H-.S. Philip Wong, and K. C. Saraswat, “Metal-induced dopant (boron and phosphorus) activation process in amorphous germanium for monolithic three-dimensional integration”, Journal of Applied Physics 106, 074510 (2009).
FIG. 1 herein reproduces FIG. 3(b) from the Park et al. Applied Physics Letters 93 publication and shows SIMS (secondary ion mass spectrometer) and SRP (spreading resistance profiling) data (carrier concentration as a function of depth) of an N+/P junction on epi-Ge annealed at 360° C. for 10 minutes with Co and at 600° C. for 1 minute without Co. The Figure illustrates the distinction between P implantation and Co-induced crystallization.
A problem that arises when considering the fabrication of transistors using a Group III-V compound semiconductor (composed of elements from Group III and Group V of the periodic table of elements) is that due at least to a reliable silicide process, the self-aligned integration of a Group III-V transistor (e.g., a metal oxide semiconductor field effect transistor or MOSFET) is difficult to accomplish. This difficulty can affect the ability to fabricate low resistance electrical contacts to the source and drain regions of the transistor.